KBC Status Register

Keyboard Controller Status Register

The Intel 8042 or equivalent keyboard controller which is directly accessible via ports 0x60 and 0x64 makes certain information available on its status register. This can be examined at any time as a read of port 0x64. In particular the register includes two bits to indicate whether the controller can be written to (bit 1) and whether it has data waiting to be read (bit 0).

The Status Register

Bit Meaning on AT Systems Meaning on PS/2 Systems
7 0 = No parity error (ph)
1 = Parity error (ph). The last byte read from the serial link had even parity and only odd parity is allowed (upc)
0 = The last byte received from the keyboard correctly had odd parity.
1 = The last byte recived from the keyboard incorrectly had even parity. 0xFF has been loaded into the the output buffer waiting to be read from port 0x60, or if bit 6 is also set to 1, a byte sent by the KBC to the keyboard was received at the keyboard with a parity error. (kadc)
6 0 = No reception error (ph)
1 = Keyboard did not finish receiving a byte (ph) The keyboard began sending information but did not complete the transmission in time (upc)
0 = No timeout has occurred.
1 = A receive or a transmit timeout occured (either of the two conditions for the AT bits 6 and 5). If a receive timeout has occurred 0xFF will have been loaded into the the output buffer waiting to be read from port 0x60. Only this bit will be set to 1. If, instead, the keyboard has indicated that it received a byte with a parity error 0xFE will have been placed in the output buffer waiting to be read from port 0x60. This bit and bit 7 will have both been set to 1. (kadc)
5 0 = No transmission error
1 = Transmission error detected (ph) This will occur if the time to transmit one byte is too long or if the byte was sent but the response exceeded the timeout. This error also occurs if the response to a timeout has a parity error. Then both parity and transmit error bits are set (upc)
When there is a byte in the output buffer (as indicated by bit 0 being set to 1) this bit will be zero if the byte is from the keyboard and will be set to one if the byte is from the mouse. (kadc)
4 0 = Keyboard inhibited (ph) On password controlled systems 0 indicates the keyboard is inhibited until the password has been verified (upc)
1 = Keyboard not inhibited (ph)
As AT systems
3 0 = Internal input buffer holds data from port 0x60
1 = Internal input buffer holds a command from port 0x64
As AT systems
2 0 = System flag status bit, indicates reset by power on (ph)
1 = System flag status bit after successful controller self test (ph) This bit can also be set from the system flag bit of command 0x60 (not to be confused with port 0x60) (upc)
As AT systems
1 0 = Input buffer vacant and can be written to (ph)
1 = Input buffer occupied and cannot accept another command or data byte until the controller has processed the one it already has (ph)
As AT systems but on the type 2 controller this bit is also set to one while transmitting to the keyboard or mouse. After the last bit has been sent this bit returns to zero. (kadc)
0 0 = Output buffer vacant and has nothing to read (ph)
1 = Output buffer occupied and has a byte waiting to be read (ph)
As AT systems


In the text above sources are

  • (kadc) - IBM PS/2 Reference Manual: Keyboard and Auxiliary Device Controller
  • (upc) - The Undocumented PC, second edition - Frank van Gilluwe
  • (ph) - PC Programmer's Handbook, second edition
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